Intel 48-core and TILE-Gx Cloud processor.

Intel gave a look at its long-term future by showing the Single-chip Cloud Computer (SCC), a 48-core processor, the chip is an offspring of a very early 100-core project and shares its unique "network" approach that keeps each one of the full x86 cores communicating with each other at full speed, earning its cloud computing-inspired name. The new model, however, is extremely efficient: it uses unspecified new energy management to consume no more than 125W at peak load and as little as 25W, even when all 48 cores are active.

The primary obstacle to the processor is software optimization, Intel says. Most software is only designed to address a much smaller number of cores and needs to be reworked to operate with many tasks running in parallel. Java-based Hadoop has been used to port over cloud computing apps, but Intel fully expects CPUs on this magnitude to reach the home and will need a different software set. Apple's Grand Central Dispatch in Mac OS X Snow Leopard is partly meant to address this limit by simplifying the process of rerouting tasks to particular cores.

Among the advances believed possible by the SCC are "vision" apps that use the parallelism to recognize the environment with a camera and trigger interactions or overlays without needing input. A store could show an accurate 3D model of clothes on a customer's body in real-time, for example.

Some unnamed features of the SCC are due to show up in Intel's 2010 processor line, but the semiconductor firm hasn't said how soon production designs more closely resembling the prototype will be ready. The first mainstream six-core processors, including Core i9 and a companion Xeon line, won't ship until early next year. Full eight-core processors are due later that year.

If you thought Intel's plans to embed eight cores in its high-end processors were a bit too out there, you'll find that the latest processor developed by semiconductor start-up Tilera is even more of an extreme. Packing 100 1.25GHz to 1.5GHz cores on a single chip, the Gx100 brings parallel processing to the extreme thanks to a new architecture that minimizes the bus bottleneck in today's multi-core processors.

Chip makers are constantly pushing for faster processors, but clock speeds can only be pushed so far. As a result, the semiconductor industry has opted to pack multiple processors on a single chip and dividing the workload in equal parts whenever this is possible — that's the gist of parallel computing.

Graphics processing units are a common example of a "multi-core" chip that can process hundreds of independent data streams in parallel: each stream is processed separately and the result is then output on the screen. Programmers are starting to harness the parallel data processing capabilities of GPUs, and by doing so they can often speed up their data crunching by tens or even hundreds of times.

However GPUs, especially the older models, have limited flexibility and are built for speed, not precision (if a single pixel is a little bit off color, people won't usually notice). Even though GPU makers are developing better architectures for using them as data crunchers, they still remain far from a general-purpose processor, making them able to speed up only certain tasks.

This is when the Tile Gx100 comes in. The Gx100, as Tilera chief technical officer Anant Agarwal explained, is a chip that can run off-the-shelf programs almost unmodified, offering at least four times the compute performance of an Intel Nehalem-Ex while burning a third of the power. In other terms, it makes GPU-like massive parallel processing available on a general-purpose chip.

Because the chip is general-purpose, programmers can recompile and run applications designed for Intel's x86 architecture on Tilera's processor without the need for further adaptation.

The key idea behind the design of the chip was a simplified architecture that eliminates the on-chip bus interconnect through which information must flow in most multi-core CPUs. This was replaced with a mesh network architecture, which involves placing a communication switch on each processor and arranging them in a grid-like fashion.

The bus architecture was a performance bottleneck that reduced the amount of data that could travel from the various cores and forced engineers to limit the number of cores on each chip. But because of this new architecture, Tilera says it can cram in as many as 100 cores on a processor without running into the bus-bandwidth limit.

The 100-core processor, fabricated using 40-nanometer technology, is expected to be available early next year, but won't be supported by Windows 7. For that, consumers will have to wait for Intel's 80-core version, which the IT giant promised to deliver to consumers sometime during the next five years.

TILE-Gx Processors Family

The TILE-Gx™ processor family processor brings 64-bit multicore computing to the next level, enabling a wide range of applications to achieve the highest performance in the market. This latest generation processor family features devices with 16 to 100 identical processor cores (tiles) interconnected with Tilera's iMesh™ on-chip network. Each tile consists of a complete, full featured processor as well as L1 & L2 cache and a non-blocking switch that connect the tiles into the mesh. As with all Tilera processors, each tile can independently run a full operating system, or, multiple tiles taken together can run a multiprocessing OS like SMP Linux.

The TILE-Gx family processor slashes board real estate requirements and system costs by integrating a complete set of memory and I/O controllers, therefore eliminating the need for an external north bridge or south bridge. TileDirect™ technology provides coherent I/O directly into the tile caches to deliver ultimate low-latency packet processing performance. Tilera's DDC™ (Dynamic Distributed Cache) system for fully coherent cache across the tile array enables scalable performance for threaded and shared memory applications.

The TILE-Gx processors are programmed in ANSI standard C and C++, enabling developers to leverage their existing software investment. Tiles can be grouped in clusters to apply the appropriate amount of horsepower to each application. Since multiple virtualized operating system instances can be run on the TILE-Gx simultaneously, it can replace multiple CPU and DSP subsystems for both the data plane and control plane.